Publications - (selected)

This work aims to propose an area and power efficient pulse shrinking time-to-digital converter (TDC) for use in temperature sensor. The time difference between a digitally controlled delay cell (DCDC) output and a fixed reference input is compared in generating a pulse whose on-time shrunk depending upon the choice of DCDC select lines. Eventually, the pulse is fed to a gated ring oscillator to note the time difference and then an asynchronous counter to record the generation of digital code. Simulation results in a 90-nm CMOS and 1.1 V power supply Vdd indicate a power consumption 409 μW while attaining a competitive resolution of 25 ps. Besides, linearity is confirmed by achieving a DNL value of 1.03 (LSB) and INL of 1.38 at 1.1 V Vdd. Additionally, Monte Carlo study indicates a standard deviation within 0.5% to suggest robustness of the design.

This article presents a multi-conversion mode temperature sensor exploiting channel length modulation coefficient λ of MOSFET. To achieve this an inverter interlaced cascaded delay cell (IICDC) and gated ring oscillator (GRO) having different channel lengths are used to design a temperature-to-time converter (TTC) followed by a time-to-digital converter (TDC). The proportional-to-absolute-temperature (PTAT) nature of the delay cells provides sharp changes in current ratio with temperature and so does the propagation delay ratio of the delay cells. This ensures change in temperature code with temperature shift. The programmability option in TTC allows the sensor to exhibit eight different resolution options using eight different conversion time modes. At 90-nm CMOS process, the layout area is 0.014 mm2 and the power is noted to be 148 μW across the modes at 27°C and 0.8 V supply voltage. This confirms an energy/conversion between 0.145 and 18.63 nJ while the resolution is between 0.743°C and 0.0058°C over –60°C to 80°C. Eventually, the conversion time ranges between 0.982 μs and 125.76 μs and a method is adopted to terminate the sensor working after each sampling is completed. The sensor can be used as a part of system-on-chip (SoC) for precise monitoring of the self-heating problems with multiple sampling rate options.

This work suggests an all-digital temperature sensor with a high sampling rate that is based on a time-to-digital converter (TDC). Two on-chip voltage-controlled oscillators (VCOs) are used in the design of the sensor core, which senses temperatures between −40∘C and 200∘C. For digital code conversion, the outputs of the VCO are fed into two asynchronous counters. In both low- and high- resolution modes, the error following two-point calibration is observed between −1.08∘C and +1.06∘C. The sensor’s ability to function in both high- and low-resolution modes based on conversion time is an important feature. At a sampling frequency of 0.19MHz, the maximum resolution achieved is 0.18∘C. Additionally, the sensor has control logic built in to turn off the sensing as soon as the conversion is complete. At 90-nm process, 1.1V supply voltage and 27∘C, the proposed sensor occupies 0.044mm2 and consumes 817.5 μW.

This work presents a fully integrated, self-clocked temperature-to-digital converter-based smart temperature sensor for thermal monitoring of SoC for self-heating problem. The design utilizes the channel length modulation coefficient λ with MOSFET sensing followed by a time-to-digital converter (TDC). The proposed method considers the ratio of saturation currents of two nMOSFETs with constant gate voltages but different gate lengths. At a CMOS process of 90-nm and supply voltage of 1.1 V, the sensor occupies a small area of 0.047 mm2. The sensor further attains a resolution of 0.036OC over a temperature range of −40OC to 100OC and limits the inaccuracy between −0.79OC and 0.78OC after two-point calibration.

This work presents an all-digital Programmable Delay Cell (PDC)-based time-domain smart temperature sensor exploiting the channel length modulation coefficient λ. For the first time the work has been described to establish the choice of multimode conversion options in the time-domain architecture of temperature sensor. The sensor incorporates a PDC and a time-to-digital converter (TDC) for the generation of temperature code. The different channel lengths of the PDC and Gated Ring Oscillator (GRO) delay elements of the TDC ensure the precise operation of the sensor. The proposed design provides a novel approach for the generation of variable resolution options having different sampling rates. At 90-nm CMOS process and 1.1 V supply voltage, the sensor occupies 0.015 mm2 and operates over a span of −60°C to 120°C. Additionally, multimode conversion time allows the sensor to be tuned to a small value of energy/conversion at 27°C. This confirms to 0.38 nJ and 3.13 nJ at modes M0 and M7, respectively. Besides the sensor obtains a resolution 0.747°C and 0.093 °C at a conversion time of 0.669 μs and 5.5 μs, respectively.

This work presents an all-digital time-mode subthreshold temperature sensor for monitoring SoC self-heating problem. The sensor incorporated a low-power differential inverter interlaced cascaded delay cell followed by a gated ring oscillator with different temperature coefficients of −1736.10 and −5880.33 ppm/∘C, respectively. The differential inverter interlaced cascaded delay cell and XOR gate produce a temperature-dependent large delay pulse, whereas the gated ring oscillator produces temperature-dependent output code for each point of temperature within the delay pulse generated by the differential inverter interlaced cascaded delay cell and XOR. The corresponding temperature code is recorded by an asynchronous counter. At 90-nm CMOS process and 0.6/0.3V supply voltage Vdd, the sensor occupies 0.009mm2 and consumes only 876nW at 27∘C. The sensor has a sampling rate of 52.16KS/s and the resolution is noted to be 0.40∘C for a temperature span of 0–100∘C. Besides, the proposed design achieves a very small energy/conversion of 17 pJ, which ensures 2.72 pJ × C2 and 0.13 nJ%2 resolution FoM and inaccuracy FoM, respectively.

Digital subsystem prefers CMOS process, but it is difficult to manage speed and average power (Pavg) trade-off in each era with power supply voltage (Vdd) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block of a SerDes, namely, the latch. However, available CML circuits consume significant Pavg and suffer from rapid input slewing. Typically, fast switching inputs enable current flow to effective supply voltage VP and overcharges output. In fact, Vp is different than externally applied Vdd and oscillates with time as and when an abrupt current is drawn. This affects delay td and introduces jitter. The topic presents a new latch for SerDes interface using a new current steering circuit and coupled to a power delivery network (pDN). The significant point is to attain an almost constant td in comparison to conventional designs while the Vdd changes. The post-layout results at 0.09-μm CMOS and 1.1 V Vdd indicate that the Pavg and td are 339.5 µW and 61.9ps, respectively, at 27°C. Surprisingly, the td variation is noted to be minimum and the power supply noise induced jitter is around 1.5 ns when Vp close to the circuit varies due to sudden current.

Managing the speed and power trade-off is becoming increasingly challenging as the power supply voltage (Vdd) is scaled down in each era. Existing logic circuits that address the trade-off require more power. A new logic circuit made up of one PMOS and two NMOS is evaluated while coupled to a typical power delivery network (PDN). Simulated in a 0.09 µm CMOS, the present circuit not only reduces the supply current but also achieves a constant delay than the CSL, MCML and CS-CMOS while the Vdd switches from 0.7 to 1.1 V. Besides, the power consumption and delay sustain a shift of 0.14µW and 0.3ps, respectively, following a 1OC change in temperature. However, the power consumption reduces by 0.2µW for a Vdd drop of 1mV. But the effective supply voltage close to the circuit fluctuates as the PDN draws a sudden high current. This causes the delay to change and induces jitter in the output swing. The jitter introduced for a current ramp 0–40A in 10ns is 6.7ps. The usefulness of the present design is also observed by designing a latch, master-slave flip-flop (FF), frequency divider (FD) and ring oscillator (RO). Comparing the latch, FF, FD and RO built using the conventional, proposed designs and simulated in a 0.09-µm CMOS show the lowest power and delay.

A three bit digitally controlled differential delay circuit is investigated in this work. The circuit is coupled to a normal high current power delivery network (PDN), which is capable of coming up from sleep mode (0A) to 10 or 30A or else 50A in 10ns. Simulated in a 0.09-μm CMOS process and power supply voltage (Vdd) of 1.1V, the proposed circuit in post-layout can operate from 435.5ps to 152.2ps. The corresponding input vector (CBA) during this period switches from 000 to 111. Further, there are also intermediate states as the delay varies between the said ranges. These values of delay being dependent on the input vector has been noted to reduce monotonically. In addition to that, the post-layout delay sustains a shift of 4.0 and 6.5ps for NN and SS process corner, respectively, following a ±10∘C change in temperature. But an abrupt high current I(t) pumped into the chip causes the voltage (Vp) near the device to drop due to PDN. It also fluctuates with the natural frequency of PDN. The noise so developed induces jitter in the output swing and causes more delay between input and output in comparison to the circuit designed with zero noise in power supply. The jitter achieved for a current ramp I(t) of 0–50A in 10ns for the two vector CBA happens to be around 5.0 and 4.4ps, respectively. The current ramp also generates power supply noise of 0.468V occurring close to the silicon chip. This, in turn, corresponds to a Vp of 0.642V near the die, appearing to be much less than the required Vdd of 1.1V. Therefore, the delay is found to be affected significantly due to the sudden current ramp. It is also noted that a constant DC voltage of 0.642V has quite different effect on delay and jitter than a fluctuating AC noise having the first droop same as that DC voltage.

Multiplexer (mux) latch is one of the key components for serializer interface to admit communication at Gbps. This work describes the working of a 2:1 mux-latch coupled to a power delivery network (PDN) and a CPU core drawing abrupt current. In comparison to conventional designs, multiplexer and latch operate at the same time, which is quite different because enable inputs are imperative to start latch operation. An analytical model is also derived to understand power delay trade-off and to choose gate sizes to obtain a comparable delay without increasing power. The average power and delay in post-layout are 257.7 μW and 35 ps, respectively, in a 90-nm CMOS, power supply voltage (Vdd) of 1.1 V and a clock switching at 6.25 GHz. However, a 117OC change in temperature at distinct corner allows average power to vary between 32.8 and 64 μW. The corresponding variation is 135–183.7 μW as Vdd switches from 0.75 to 1.1 V. In addition to so, delay changes between 5-14 ps and 3–12 ps for the given change in temperature and Vdd, respectively. Nonetheless, the effective supply voltage VP oscillates with time as the CPU core draws abrupt current. The delay values due to AC noise are found to be different than VP having no noise and the corresponding jitter changes linearly as a function of noise.

Power supply voltage (Vdd) scaling in each era is making difficult to manage speed and power trade-off. Latch is a basic component in wireless and wireline communication to enable data transmission at Gbps. Conventional latches minimise the trade-off at the cost of layout area and average power (Pavg). Coupled to a common power delivery network (PDN) and a CPU core drawing abrupt current, a 2-level latch is presented and evaluated to understand performance under process, voltage, temperature (PVT) and AC noise. An analytical delay model is also derived to understand Pavg- delay (td) trade-off. The delay model gives simple expression suitable for manual evaluation of td. The Pavg, td, power-delay-product (PDP) and figure of merit (FoM) in post-layout are 28.5 μW, 140.4 ps, 4 fJ and 172.3 ns×fJ×µm2, respectively, in 90-nm CMOS and 0.45 V Vdd. Nonetheless, at distinct corner the metrics change by 0.01 μW, 0.2 ps, 0.005 fJ and 0.4 ns×fJ×µm2, respectively, for 1°C shift in temperature. The variations for 1 mV drop in Vdd are 0.2 μW, 1 ps, 0.005 fJ and 1.4 ns×fJ×µm2, respectively. Despite this, the voltage close to the die VP oscillates with time as the CPU pumps current. The td due to AC fluctuating noise, namely, 1st droop, 2nd droop, so forth and DC (various voltage levels) are quite different. The Ldi/dt noise so generated due to the oscillations in VP introduces jitter in the output swing.

While trying to represent the performance metrics of a single-stage amplifier as a function of designable parameters, it is observed that the corresponding metrics form a polytope-type feasible region. Indeed, the polytope so formed is made up of performance metrics which can either be objectives or constraints. Initially, the simplex method is used to obtain an objective value that satisfies a set of constraints. Once the objective is available, the interior point-based method is used to check whether any objective lies inside the feasible region or not. The proposed design flow examines both the periphery and the interior of the polytope so generated. Henceforth, the design of an amplifier can be pointed out to be a distinctive type of optimization concern, called Nonlinear Programming (NLP). Furthermore, efficient global optimization methods have been established to yield an automated synthesis of amplifiers derived from the requirements. In this work, the formulation of the design problem for a cascode amplifier as NLP is described and analyzed. Thereafter, the optimal trade-off curves related to the performance metrics such as small signal gain (Av), unity gain frequency (UGF) or gain bandwidth product (GBWP), and power are derived in order to observe the corresponding dependencies.

This article unveils a new hybrid configuration of ring type VCO (voltage controlled oscillator) consisting of CMOS and current starved inverter to generate full voltage swing. A certain number of such inverters are cascaded alternatively to obtain the output frequency (fosc). The novelty lies in the fact that this design offers a good trade-off of power, frequency and gate count against CMOS based or current starved based design counterpart. In a 90 nm process, the highest fosc achieved for a 7th stage VCO device footprint is 1.78 GHz with a power dissipation of 44.59 µW at a supply and control voltage of 1.2 V and 1 V respectively. The simulated phase noise and output noise of the layout read to be −95.15dBc/Hz and −144.55 dB respectively measured at 1 MHz offset frequency along with the corresponding figure of merit (FOM) of −173.67dBc/Hz. In order to understand the robustness and scalability of the proposed design, the performances are observed using Monte Carlo study and as small as UMC 28 nm CMOS process.

An inverter is designed using an innovative controlled voltage swing logic and having two different current sources. The logic levels are detected by sensing the voltage drop across a termination resistance. Logic 1 is defined when both the current sources are pumping current through termination resistance, whereas a logic 0 is determined when one of the sources is pumping current. This inverter is the newest class of inverter and used in designing a ring oscillator, capable of operating at various frequencies, fosc. Varying the external load capacitance (CL) from 1 to 10 fF, the values of fosc are tuned in between 0.8 and 1.0 GHz. Mathematical equations relating fosc as a function of CL and intrinsic capacitive components (Θ) are obtained and subsequently validated using gpdk 90 nm technology CMOS process. The proposed controlled voltage swing ring oscillator is observed to draw a current of 0.716 μA at fosc close to 1.0 GHz. The corresponding CL and the Θ happen to be 1.0 and 53.8 fF, respectively. The effect on fosc due to layout geometries and other process parameters keep on changing only by 16% compared to a 7% change in the intrinsic values between pre and post layout for the said ring oscillator. Lastly, a linear empirical relation is obtained to indicate fosc as a function of both CL and the power supply voltage (Vdd).

In this paper a method is proposed to derive an equation for the oscillation frequency and amplitude of a ring oscillator built using two different current sources. Taking into consideration the transistor’s region of operation, the proposed method estimates the variation in oscillation frequency because of externally added load capacitance, supply voltage and number of stages. The analytical model so proposed is justified using 0.18 μm and 0.09 μm CMOS technology for a 5 stages ring oscillator. Indeed, the estimated oscillation frequency agrees with the simulated one, while the error was within 5%.

Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology and power supply voltage (Vdd) of 1.1 V, the post-layout delay was noted to be 227 ps During this time, differential signals at the input are switching at 1GHz while the rise, fall times are about 0.1ns The power thus dissipated corresponds to 235 μW. But, delay changes by about 0.4–0.9 ps at every process corner while temperature increases by 1OC. The corresponding variation for 1mV drop in power supply voltage is 0.1–0.4ps In addition to that, a change in temperature enables the average power to fluctuate between 192.8 and 264μW, whereas, 0.6μW for 1mV drop in power supply voltage. The study of 500 runs Monte-Carlo analysis for a NN process indicates an almost identical behavior with the no skew data in post-layout. The rms jitter is within 0.01–0.3ps while the delay per mV change in power supply is 0.21 ps/mV. But a sudden current drawn by the CPU causes the voltage VP close to the die to oscillate. This enables the delay to vary than those obtained with zero power supply noise. The sudden current also introduces jitter in the output swing. The jitter so induced varies linearly with the AC first droop.

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be 471.6 μW and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <;10-12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC.

This article proposes a design approach of common source (CS) amplifier based Voltage Controlled Oscillator (VCO) to derive higher oscillation frequency. The working feature is such that, the active load of CS amplifier is varied to modulate the flow of current based on a bias circuit steered by an external controlled voltage (Vctrl), which controls the delay of each stage and thereby regulates the oscillation frequency. The circuit is designed and analyzed on Cadence Virtuoso platform at a supply voltage of 1.2 V for 90 nm CMOS to read a device footprint of 0.105 mm2, which offers a power burn and frequency of 2.092 mW and 9.21 GHz respectively with a phase noise and output noise of − 137.9 dBc/Hz and − 168.40 dB at 1 MHz offset frequency. To justify the reliability of the circuit we have conducted worst case analysis by considering effect of power delivery network (PDN) and corner variation along with 500 runs of Monte Carlo. The design is also introduced under 28 nm UMC to validate its scalability with technology trends.

On switching a transmitter at gigahertz rate, the data at the receiver's end gets distorted in terms of pulse width and voltage due to line loss and dispersion originating from channel electrical characteristics. Signalling using current sources is an established approach for high frequency applications, but different receiver circuits have been proposed to effectively sense the low voltage swings around some reference voltage, VT. At first, the VT is identified at the receiver's input by a unique method and the corresponding value is found to be 0.822 V. Thereafter, a signalling scheme has been proposed to have two different current sources capable of generating a low voltage swing around VT at the receiver's end and at the same time compensating the line loss of the channel. The low voltage swings around VT cause leakage current to increase. The proposed methodology reduces the constant short circuit current due to low voltage swings around VT almost close to 0 from 56 μA for 60 mV swing. The PVT analyses of the VT determination circuit and the proposed signalling scheme indicate the sensitivity of the proposed approach while operated at 1 GHz switching frequency. Further, the crosstalk analysis for a 60 mV swing around VT at 180 nm CMOS process and single ended point to point drivers portrays that the desired s/h (s is the edge to edge space between two traces and h is the corresponding height from the ground plane) has to be greater than 2.3 for crosstalk noise to be below the critical value. Measurements and simulations also indicate that the proposed methodology for terminated design consumes only 1.08 mW for data transfer over point to point interconnects compared to conventional schemes.

In multi-Gbps chip-to-chip signalling, the transmitter clock jitter limits the maximum possible data speed for a required Bit Error Rate (BER). If the communicating channel between transmitter and receiver is lossy and noisy, the waveform of the driven signal, detected at the receiver chip changes completely due to the properties of channel made of copper interconnect. The reflection noise, generated at various points of the channel due to impedance mismatch, makes identification of the signal very difficult at the receiver. Due to that, it is challenging to send high frequency signals (pulse width of
<
100
psec
corresponding to
>
10
Gbit
/
sec
data rate) between two chips in manufacturable environment for high volume products with various process parameters. In this work, we have discussed two methods of defining threshold voltage of receiver chip by which it is possible to send a square pulse of 15 picoseconds or less width (that may corresponds to 66 Gbit/sec or more) over a unmatched lossy channel. The receiver chip of proposed method uses a comparator, which is fed by the received oscillatory signal (Signal-A) and RC delayed version (Signal-B) of it. In order to avoid needless switching at the output, we also have incorporated conventional comparator hysteresis loop such that the feedback path will control the threshold depending on the comparator output.

As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible.

The biggest motivation to study reversible technologies is that, it is considered to be the best potential way to improve the energy efficiency than the conventional models.

In a computational model, that uses transitions from one state of the abstract machine to another, a necessary condition for reversibility is that, the relation of the mapping from states to their successors must be one-to-one. In these works, the primary focus of design is to optimize number of reversible gates and garbage outputs. The calculation of number of gates is not a good option to check the complexity of a circuit as each gate has different architectural complexity decided by a parameter called quantum cost. Delay, hardly addressed in the existing works available in literature, is another good parameter to be optimized for fast reversible computation. In this work, we have presented novel designs of basic sequential circuits like latch that are optimum in terms of delay, quantum cost and garbage. We have also demonstrated quantum cost efficient D-FF, SR-FF, JK-FF & T-FF, along with their master slave …

Analog-to-digital converters (ADCs) are needed in all those applications, which interface with the analogue world and exploit the digital processing of data. As digital processing is more and more gaining ground over analogue signal processing, the importance of ADCs correspondingly increases.